As DRAMs increase in memory cell density, there is a continuing challenge to maintain sufficiently high storage capacitance despite decreasing cell area. Additionally, there is a continuing goal to further decrease cell area. One principal way of increasing cell capacitance is through cell structure techniques. Such techniques include three-dimensional cell capacitors, such as trenched or stacked capacitors. Yet as feature size continues to become smaller and smaller, development of improved materials for cell dielectrics as well as the cell structure are important. The feature size of 256 Mb DRAMs will be on the order of 0.25 micron, and conventional dielectrics such as SiO.sub.2 and Si.sub.3 N.sub.4 might not be suitable because of low dielectric constants.
Highly integrated memory devices, such as 256 Mbit DRAMs, are expected to require a very thin dielectric film for the 3-dimensional capacitor of cylindrically stacked or trench structures. To meet this requirement, the capacitor dielectric film thickness will be below 2.5 nm of SiO.sub.2 equivalent thickness. Chemical vapor deposited (CVD) Ta.sub.2 O.sub.5 films are considered to be very promising cell dielectric layers for this purpose, as the dielectric constant of Ta.sub.2 O.sub.5 is approximately three times that of conventional Si.sub.3 N.sub.4 capacitor dielectric layers. However, one drawback associated with Ta.sub.2 O.sub.5 dielectric layers is undesired leakage current characteristics. Accordingly, although Ta.sub.2 O.sub.5 material has inherently higher dielectric properties, as-deposited Ta.sub.2 O.sub.5 typically produces unacceptable results due to leakage current.
Densification of Ta.sub.2 O.sub.5 as deposited has been reported to significantly improve the leakage characteristics of such layers to acceptable levels. Prior art densification includes exposing the Ta.sub.2 O.sub.5 layer to extreme oxidizing conditions. Undesirably, however, such has a tendency to form an SiO.sub.2 layer intermediate or between the lower electrode (typically polysilicon) and the Ta.sub.2 O.sub.5. Further and regardless, a thin SiO.sub.2 layer will also typically inherently form during the Ta.sub.2 O.sub.5 deposition due to the presence of oxygen at the polysilicon layer interface. It is desirable to remove or eliminate this SiO.sub.2 layer intermediate the Ta.sub.2 O.sub.5 and polysilicon layers, yet allow for such desired densification.
One prior art technique includes exposing the polysilicon layer to rapid thermal nitridation just prior to deposition of the Ta.sub.2 O.sub.5 layer. Such is reported by Kamiyama et al., "Ultrathin Tantalum Oxide Capacitor Dielectric Layers Fabricated Using Rapid Thermal Nitridation prior to Low Pressure Chemical Vapor Deposition", J. Electrochem. Soc., Vol. 140, No. 6, June 1993 and Kamiyama et al., "Highly Reliable 2.5 nm Ta.sub.2 O.sub.5 Capacitor Process Technology for 256 Mbit DRAMs", 830-IEDM 91, pp. 32.2.1-32.2.4. Such rapid thermal nitridation includes exposing the subject polysilicon layer to temperatures of from 800.degree. C. to 1100.degree. C. for sixty seconds in an ammonia atmosphere at atmospheric pressure. The nitride layer acts as a barrier layer to oxidation during Ta.sub.2 O.sub.5 deposition and subsequent high temperature densification processes to prevent oxidation of the underlying polysilicon electrode. However, such processing can create other problems as explained with reference to FIGS. 1 and 2.
A prior art semiconductor wafer fragment in process is indicated in FIG. 1 with reference numeral 10. Such comprises a bulk monocrystalline silicon substrate 12 having word or gate lines 14, 16, 18 and 20 formed thereover. Exemplary diffusion regions 15 and 17 constituting a transistor source or drain are provided as shown. An area or region 22 of wafer fragment 10 comprises a memory array area while a region or area 24 constitutes some area typically peripheral to the memory array. A first insulative layer 26, for example borophosphosilicate (BPSG) glass, is formed over and about gate lines 14-20. Exemplary conductive plugs 28 and 30 extend upwardly from diffusion regions 15 and 17 within substrate 12 between the illustrated gate lines within insulating material layer 26 to the upper surface of insulating layer 26. Such plugs are heavily doped with 1 phosphorus to a concentration of, for example, greater than or equal to 1.times.10.sup.21 atoms/cm.sup.3 to achieve acceptable conductivity.
A second insulative layer 32, again typically BPSG, is formed over first insulative layer 26 and polysilicon plugs 28 and 30. An opening 34 for a capacitor is etched within layer 32 over polysilicon plug 28 within array region 22. A lower or inner capacitor electrode 36 is formed within opening 34. Such again preferably comprises heavily phosphorus doped polysilicon, such as hemispherical grain polysilicon. Nitridation would then occur to form a very thin (i.e., less than 50 Angstroms) layer of Si.sub.3 N.sub.4 (not shown).
Unfortunately, the high nitridizing temperature has the effect of out diffusing phosphorus from polysilicon into layer 32 where polysilicon plugs formed elsewhere on the wafer are not covered with lower capacitor electrode material, such as plug 30. Such is shown by outline 40 in region 24. Although layer 32 in the typical prior art example does include phosphorus doping, the phosphorus concentration within the polysilicon plugs is considerably greater, leading to the out diffusion and localized greater concentration of phosphorus within layer 32. Out diffusion of this nature is not problematic where the polysilicon plugs underlie capacitor electrode material, as both layers in such instance typically constitute polysilicon which is heavily doped with phosphorus.
Referring to FIG. 2, a Ta.sub.2 O.sub.5 layer 42 is formed over the substrate and subsequently etched or planarized back to form said dielectric layer over the lower or inner capacitor electrode 36. As above, such layer is then subjected to oxidation conditions which densify said layer to form a desired capacitor dielectric layer. Unfortunately, the higher doped phosphorus region 40 within the BPSG layer immediately proximate the polysilicon plugs results in an air bubble or void 44 forming within BPSG layer 32. This also has a tendency to inherently lift layer 32 upwardly and off of the plug. Such is highly undesirable. The formation of this bubble/void is also a function of the stress in the BPSG as well as the geometry of the underlying encapsulated gate line or other features, but is aggravated by the high temperature processing associated with the nitridation and Ta.sub.2 O.sub.5 densification steps.
It would be desirable to improve upon such prior art processes, enabling utilization of Ta.sub.2 O.sub.5 layers in capacitor constructions. Although the invention was motivated from this perspective, the artisan will appreciate applicability in other areas of semiconductor processing with the invention only being limited by the accompanying claims appropriately interpreted in accordance with the Doctrine Of Equivalents.